This application is based upon and claims priority of Japanese Patent Application No.10-374717, filed on Dec. 28, 1998, the contents thereof being incorporated herein by reference.
The present invention generally relates to semiconductor devices and more particularly to fabrication of a semiconductor device having a shallow junction.
In the art of CMOS LSIs (large scale integrated circuits), increase of integration density, and hence increase of operational speed of the semiconductor device, has been a consistent and important target of device development. Today, LSIs are fabricated according to the so-called submicron rules or sub-quarter micron rules and the minimum pattern width in the LSI is becoming smaller than 0.2 xcexcm.
In the CMOS LSIs having such a very large integration density, it has been recognized that the so-called short-channel effect appears conspicuously. Such a short-channel effect emerges as a result of the MOS transistor operation deviating from the classical gradual approximation model. When such a deviation appears conspicuously, there arises various problems in the transistor operation such as decrease of drain current or shifting of threshold voltage.
Conventionally, it has been recognized that such a short channel effect can be reduced by decreasing the ion implantation energy or acceleration energy in the step of forming the source or drain region such that the depth of the junction formed in the semiconductor substrate is reduced.
TABLE I summarizes the acceleration energy and dose that have been used or to be used in the ion implantation process of CMOS technology of various generations in the past or in the future.
Referring to TABLE I, it should be noted that the acceleration energy is reduced with the progress of the device generation and hence device miniaturization, wherein it can be seen that the use of such a reduced ion implantation energy is particularly important in the formation of the p-type drain extension structures, which are formed by injection of B into the Si substrate by an ion implantation process. In the fabrication technology of a CMOS device of the 180 nm design rule, it should be noted that an acceleration energy of about 2 keV is used for the formation of the p-type drain extension structure, while in the case of a CMOS device fabricated according to the 130 nm design rule, an acceleration energy of about 0.5 keV may be used.
Conventionally, an ion implantation process has been conducted such that impurity ions are implanted into a Si substrate through a thin oxide film formed on the surface of the Si substrate. By employing such an approach, the impurity elements that have failed to enter the substrate and remaining on the surface of the oxide film in the form of precipitates are removed easily by conducting a cleaning process or by removing the oxide film itself, and the reliability of the semiconductor device is improved.
On the other hand, such an approach to implant the impurity ions into the substrate through such an oxide film causes a problem, particularly in the advanced high-speed CMOS devices having a very shallow LDD (lightly doped drain) structure, in that it is necessary to use a relatively large energy for causing the impurity ions to reach the Si substrate after traversing through the oxide film. Because the use of large acceleration energy induces a large standard deviation in the particle energy, it should be noted that the depth of the junction formed in the Si substrate tends to become deep. This problem becomes particularly acute in the formation of the p-type diffusion region which is formed by an ion implantation of B.
FIG. 1 shows the accumulated dose of B for the case in which B is implanted to a Si substrate in the form of B+ with an acceleration energy of 0.5 keV. It should be noted that the accumulated dose of FIG. 1 represents the ratio of the B atoms included in the Si substrate in the region between the substrate surface and the designated depth over the entire amount of the B atoms implanted in the Si substrate. Thus, the accumulated dose is calculated from the depth profile of B in the Si substrate obtained by an SIMS (secondary ion mass spectroscopy) analysis. In view of the fact that the depth profile of B in an SiO2 film and the depth profile of B in an Si substrate are more or less the same, the accumulation dose of FIG. 1 can be regarded as the proportion of the B atoms captured by an SiO2 film covering the Si substrate with a desired thickness.
In the process technology of the state of the art, an SiO2 film can be formed on a Si substrate with reliability only when the thickness thereof is more than about 2 nm. Assuming that the thickness of the SiO2 film is 2 nm, FIG. 1 indicates that about 50% of the B atoms are captured by the SiO2 film. In other words, the efficiency of B injection into the Si substrate becomes substantially poor in the process technology available today, provided that the ion implantation process is conducted through a thermal oxide film. When the efficiency of injection of the impurity element into the Si substrate is low as such, the impurity concentration level in the Si substrate cannot be increased as desired, and the diffusion region tends to show an increased resistance. Because of this, the process technology of forming a thin oxide film on a Si substrate with a thickness of less than 2 nm is now becoming a key technology in the fabrication process of extremely miniaturized, high-speed semiconductor devices characterized by a very shallow junction.
Conventionally, it has been realized that the processing of a Si substrate surface by an oxidizing agent to form a chemical oxide film is effective for forming such a desirable, very thin oxide film. For example, it is possible to form a chemical oxide film with a thickness of about 1.2 nm by treating the surface of the Si substrate by a nitric acid.
It should be noted that the wet treatment process used for forming such a chemical oxide film is generally conducted by a solution containing hydrogen peroxide. For this purpose, various chemical agents listed below in TABLE II are known, including HPM (hydrochloric peroxide mixture), SPM (sulfuric acid peroxide mixture), and APM (ammoniac peroxide mixture).
Thus, it has been thought that the desired low energy ion implantation of the impurity element may become possible by forming such a thin chemical oxide film on the surface of the Si substrate and by conducting the ion implantation process through the thin chemical oxide film.
In the experimental investigation that constitutes the foundation of the present invention, however, the inventor of the present invention has discovered unexpectedly that the diffusion of the B atoms is substantially facilitated in the Si substrate when the B atoms are introduced into the Si substrate by a low-energy ion implantation process conducted through such a thin chemical oxide film. As a result of the facilitated diffusion, the B atoms penetrates deeply into the Si substrate. Although the exact mechanism of phenomenon is not well understood at the moment, it is plausible that the point defects associated with the Sixe2x80x94O dangling bonds on the surface of the chemical oxide film are injected into the Si substrate at the ion implantation process together with the impurity element.
Thus, in the case the impurity ion implantation is conducted in the state that the surface of the Si substrate is covered by a thin chemical oxide film, the injected impurity ions penetrate deeply into the substrate even in the case the ion implantation process is conducted under a low acceleration energy. Thereby, the junction defining the bottom edge of the diffusion region is located at a substantial depth in the substrate and the semiconductor device thus formed becomes vulnerable to short channel effect.
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and a fabrication process thereof wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a fabrication process of a semiconductor device including an ion implantation step conducted under a low acceleration energy, wherein the diffusion of the impurity element thus introduced into a semiconductor substrate is effectively suppressed.
Another object of the present invention is to provide a semiconductor device having a shallow junction.
Another object of the present invention is to provide method of fabricating a semiconductor device, comprising the steps of:
introducing an impurity element into a Si substrate by an ion implantation process with an energy set such that the depth of a junction formed in said Si substrate by said impurity element is less than about 40 nm; and
annealing, after said step of ion implantation process, said substrate;
wherein said method further includes a step of removing an oxide film from a surface of said Si substrate before said step of ion implantation process.
Another object of the present invention is to provide a method of fabricating a semiconductor device, comprising the steps of:
forming a chemical oxide film on a surface of a Si substrate;
reducing the number of Sixe2x80x94O dangling bonds existing on a surface of said chemical oxide film;
introducing an impurity element into said Si substrate through said chemical oxide film under an acceleration energy lower than about 0.5 keV; and
annealing said Si substrate thus introduced with said impurity element.
Another object of the present invention is to provide a method of fabricating a semiconductor device, comprising the steps of:
forming a device isolation region on a surface of a semiconductor substrate;
forming a gate oxide film on a surface of said semiconductor substrate;
depositing a gate electrode layer on said gate oxide film;
patterning said gate electrode layer to form a gate electrode; and
introducing an impurity element into said semiconductor substrate by an ion implantation process conducted under an acceleration energy lower than about 0.5 keV or lower;
wherein said method further includes a step of removing said gate oxide film from said surface of said semiconductor substrate immediately before said step of ion implantation.
Another object of the present invention is to provide a method of fabricating a semiconductor device, comprising the steps of:
forming a device isolation region on a surface of a semiconductor substrate;
forming a chemical oxide film on a surface of said semiconductor substrate as a gate oxide film;
depositing a gate electrode layer on said gate oxide film;
patterning said gate electrode layer to form a gate electrode; and
introducing an impurity element into said semiconductor substrate by an ion implantation process conducted under an acceleration energy of about 0.5 keV or lower;
wherein said method further includes a step of reducing the number of dangling bonds from a surface of said gate oxide film before said step of ion implantation process of said impurity element but after said step of patterning said gate electrode.
According to the present invention, injection of point defects into the Si substrate is effectively eliminated at the time of the low energy ion implantation process by conducting the ion implantation process in the state that the oxide film is removed from the Si substrate surface or in the state that the Sixe2x80x94O dangling bonds are eliminated from the surface of the chemical oxide film provided on the Si substrate surface. Thereby, the problem of increase of the diffusion coefficient of the impurity element associated with the point defects in the Si substrate is effectively eliminated.
Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.